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2003-07-06 | Example Xfig Diagrams | Z-80 Homebrew Computer - Mainboard Schematic

The entire reason why I started using Xfig was because of this schematic:

5 0 1 4 2 Lts i/o Lamps 2.2k B CLK 5+ GND A 8 bit print 3 Lts LEDs I/Oext. I/O ext. LEDs Lts kpd. i/o Printer Port 11 2.2k 5+ 5+ 2.2k UP DN 5+ 330 1Mhz OSC 330 2a4/LTS i/o BR BW BusA SigB BA8 BA3 Mem I/O Lts I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1 I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1 13 22 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 D4 D6 D7 CS WR A9 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND D3 D5 A10 RD A8 5+ 21 20 19 17 18 13 22 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 D4 D6 D7 CS WR A9 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND D3 D5 A10 RD A8 5+ 21 20 19 17 18 2816 13 22 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 D4 D6 D7 CS WR A9 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND D3 D5 A10 RD A8 5+ 21 20 19 17 18 2816 13 22 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 D4 D6 D7 CS WR A9 A7 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 GND D3 D5 A10 RD A8 5+ 21 20 19 17 18 2816 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1 74154 S0 S1 S6 G2 AD AC AB AA 5+ S7 S8 S9 S10 GND G1 S15 S14 S13 S12 S11 S5 S4 S3 S2 13 20 22 21 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 19 18 17 74154 S0 S1 S6 G2 AD AC AB AA 5+ S7 S8 S9 S10 GND G1 S15 S14 S13 S12 S11 S5 S4 S3 S2 13 20 22 21 23 24 2 3 4 1 6 5 7 8 9 12 11 10 16 15 14 19 18 17 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 D2 D7 D6 CE Z-80 PIO 7 8 9 6 1 2 3 20 19 14 13 12 11 10 21 24 25 26 27 28 29 30 31 32 33 38 39 40 15 CTL/DAT B/A SEL A6 A5 GND A0 A STB B STB B6 B2 5+ B RDY INT EN OUT INT INT EN IN B0 B1 B3 B4 B5 RD B7 IORQ M1 D5 D4 D3 CLOCK A7 A3 A1 A2 A RDY D0 D1 A4 37 36 35 34 5 4 16 17 18 22 23 1 2 5 5+ 14 13 10 9 8 GND 74LS00 3 4 6 7 11 12 1 2 5 5+ 14 13 10 9 8 GND 74LS00 3 4 6 7 11 12 1 2 5 5+ 14 13 10 9 8 GND 74LS08 3 4 6 7 11 12 I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1 Write En ROM Sel 2 ROM Sel 1 6116 5+ 2.2 K A0 A1 5+ Design and drawings by AC https://orng.org A11 D4 D3 D6 CLOCK A15 A14 A13 A12 D5 5+ D2 D7 D1 HLT INT NMI MREQ IOREQ WR BUSACK WAIT M1 GND RESET RD A2 A3 A4 A5 A6 A7 A8 A9 A1 A10 A0 D0 Z-80 CPU 7 8 9 4 5 6 1 2 3 14 13 12 11 10 29 30 31 32 33 34 35 36 37 38 39 40 15 20 19 18 17 16 BUSREQ REFRESH 21 22 23 24 25 26 27 28 I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1 I1 O8 I2 O7 I3 O6 CS I4 GND O5 3 5 6 7 8 9 10 4 74LS244 I5 O4 I6 O3 I7 O2 O1 CS 5+ 17 16 15 14 13 12 11 20 I8 19 18 2 1

Here is the fig file

I like using XFig, because I can capture pinouts at the same time as I represent the circuit. Tracing wires on the homebrew is quite similar to tracing wires on the schematic. Perhaps the world is different now, but when I first started XFig was the only program capable of handling the complexity of the schematic. Not even Autocad for DOS (12 or so?) could make the fonts and lines correctly, or at least, not easily. Visio actually complained that the circuit was "too complicated", and that I should simplify the drawing.

The insanely large version can be printed landscape and fit to one page. It took a horribly long time to do it in The GIMP, but it did print OK. This was on a 1.7 GHz box with a gig of RAM. I'm not sure what graphics programs can handle this on Windows. The easiest is probably to use XFig with Cygwin. More on that here. For kicks, I did open it on XP with Paint, set the page setup to print to 1 sheet in landscape, and it did a pretty good job.

For an earlier hand drawn version:

orng3613579466

Some key points about the schematic:

I buffer the data lines coming off of the Z-80 by putting an inverter between the (2) 74LS244s (BR and BW).

The clock has a 330 ohm pull-up resistor. The clock goes directly into the Z-80 clock, but I buffer it with the 5th buffer using the SigB 244 to go out to the PIOs. Many parts of this circuit evolved after the initial breadboard design. I suspect that there was some kind of settling/noise issue that required this. It works now, but I don't know exactly why I didn't run the clock signal from the buffer into the Z-80 clock signal.

The Write Enable switch disables/enables writes to the EEPROM. Nowadays, I'm using EPROMs, but if you are debugging a program and the Z-80 can write to the EEPROM, it is a real drag to re-enter the bootstrap bit-by-bit. The WR output of the Z-80 is inverted, and then run into another NAND gate before it goes on to the three 2816 memories.

There is a S/R flip-flop used to debounce the reset switch on the left side of the 74LS00 (A).

The CS on the BusA 74LS244 is connected to the BUSACK line on the Z-80. I use a front panel and the BUSREQ line on the Z-80 to load the bootstrap program. Since the Z-80 bus is high impedance when BUSACK is low, I set various signals manually this way. Some lines are forced to ground or 5+. I1 and I2 are hooked up to the control panel/display for memory bank select when programming the bootstrap via the front panel.

The PC parallel port interface inverts the signal from the printer on pin 11 (db-25 connector). I put an inverter (74LS00 B) on the output to the PC, which is connected to PIO 2, output A4.

diagrams xfig homebrew z_80

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